| 摘要 |
A method of fabricating multilevel interconnects includes providing a substrate having a pixel array area and a logical circuit area, forming a first dielectric layer on the substrate, performing a first metallizing process on the first dielectric layer to form a first patterned metal layer and a second patterned metal layer above the pixel array area and the logical circuit area respectively, forming a second dielectric layer on the first patterned metal layer, the second patterned metal layer, and the first dielectric layer, performing a second metallizing process on the second dielectric layer to form a third patterned metal layer and a fourth patterned metal layer above the pixel array area and the logical circuit area respectively, wherein patterns of the fourth and the second patterned metal layer interlace to completely cover the logical circuit area, and depositing a dielectric layer on the third and the fourth patterned metal layer. |
