| 摘要 |
A watch don timer comprising a reload register 2 and a shift register 3 is disclosed. In the case where an object to be monitored is operating normally, a circuit 43 is supplied with as a reload request signal the rising timing of a monitor signal changing cyclically, which is reloaded from the reload register 2 of the shift, register 3 in synchronism with a reload request signal in accordance with the value of data located in each bit of the shift register 3. Circuits 41, 42 are adapted to detect an abnormal condition in the case where a reload request signal is given in a cycle shorter or longer than a predetermined cycle of reloading. This configuration realizes a watch dog timer with a comparatively small scale of circuit configuration in which the pulse width of the input signal is monitored, the cycle detected and the execution of a plurality of instructions monitored, while at the same time having a programmable width and cycle and a tolerable range thereof.
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