Output buffer circuit for memory device

摘要

An output buffer circuit for a memory device comprising a pull-up path including first and second PMOS transistors for forming two parallel charging paths, and a pull-down path including first and second NMOS transistors for forming two parallel discharging paths. The first and second PMOS transistors are selectively operated according to a level of an output voltage at an output terminal to perform a charging operation for a load capacitance connected to the output terminal. The first and second NMOS transistors are selectively operated according to the level of the output voltage at the output terminal to perform a discharging operation for the load capacitance through a lead inductance.