| 摘要 |
A timer apparatus which is provided with a control circuit 80, annexed to each of timers 1-1, 1-2 and 1-3 generating a control signal making the register 3 write data outputted from a CPU 50 when both a write signal 5 generated by the CPU 50 for writing data into the registers 3, and a timer single write signal 11 for specifying any of the timers, are generated, and furthermore is provided with a selection circuit 70 making each control circuit 80 generate a control signal when both the write signal 5 and a timer grouping signal 14 generated for specifying each of the plurality of timers 1-1, 1-2 and 1-3, are generated. When it is necessary that identical data be held in the respective registers 3 of the plurality of timers 1-1, 1-2 and 1-3, the identical data can be written into each of the registers 3 at the same time.
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