Method for manufacturing thin film transistor array substrate and thin film transistor array substrate for the same

摘要

A method for manufacturing a thin film transistor array substrate includes: forming a polysilicon layer on the substrate; forming a gate insulating layer on the polysilicon layer; forming a metal oxide layer on the gate insulating layer; forming a gate metal layer on the metal oxide layer; etching the metal oxide layer to define a gate; using the gate as a second mask and etching the metal oxide layer excluding a scope of the second mask; performing ion-implantation by using the gate and a remainder of the metal oxide layer as a third mask to form two lightly doped drain regions at opposite sides of the polysilicon layer; forming an insulating layer on the gate and the gate insulating layer respectively; forming a metal layer on the insulating layer and defining a drain and a source which connect to the doped drain region and the doped source region respectively.

主权项

1. A method for manufacturing a thin film transistor array substrate, comprising:
providing a substrate; forming a polysilicon layer on the substrate; forming a doped drain region and a doped source region in the polysilicon layer; forming a gate insulating layer on the polysilicon layer; forming a metal oxide layer on the gate insulating layer; forming a gate metal layer on the metal oxide layer; etching the metal layer by using a first mask to define a gate; using the gate as a second mask and etching the metal oxide layer excluding a scope of the second mask; performing ion-implantation by using the gate and a remainder of the metal oxide layer as a third mask to form two lightly doped drain regions at opposite sides of the polysilicon layer, the two lightly doped drain region being in contact with the doped drain region and the doped source region respectively; forming an insulating layer on the gate and the gate insulating layer respectively, and defining a via hole on the doped drain region and the doped source region respectively; forming a metal layer on the insulating layer and defining a drain and a source, the drain and the source being connected to the doped drain region and the doped source region respectively through the via hole.