Rebalancing in twin cell memory schemes to enable multiple writes

摘要

A system and method of operating a twin-transistor, multi-time programmable memory (MTPM) memory cell that ensures accurate reproducibility of bit values read after each of write cycle. Each multi-time programmable memory cell includes a series connection of a first transistor and a second transistor. The method includes writing, using a write circuit at select memory cell locations, initial bit values to one or more select memory cells. Then, using the write circuit, a rebalancing of a state of a parameter associated with one or more the first transistor or second transistor, at each the select memory cell, is performed. Then, an erasing cycle is performed, at each the rebalanced select memory cell, the written initial bit value. In one embodiment, the erasing cycle may first be performed prior to rebalancing. The rebalancing and erasing are to be performed prior to each bit value write cycle.

主权项

1. A method of operating a multi-time programmable memory cell, said multi-time programmable memory cell having a series connection of a first transistor and a second transistor, said method comprising:
writing, using a write circuit at select memory cell locations, initial bit values to one or more select memory cells by changing a threshold voltage state of one of said first and said second transistor relative to the other of said first and said second transistor to create a different state in a selected cell; rebalancing, using said write circuit, the threshold voltage state associated with one or more said first transistor or second transistor by changing the threshold voltage state of one of said first or said second transistor to set equal both threshold voltage states at said select memory cell, and erasing, at each said rebalanced select memory cell, said written initial bit value.