CMOS LATCH CIRCUIT

摘要

a clock process unit(10) for sequentially generating 3 phase signals( 1 - 3) to have a certain delayed time difference by receiving a clock signal(CLK); a 3 state inverter buffer(3I1) for producing a latched signal of an input data(DI) by the phase signal( 1) after sequentially loading phase signals( 1 - 3) from the clock process unit(10); a 3 state inverter buffer(3I2) for producing a latched output(LD1) from the latched data of the 3 state inverter buffer(3I1) by the phase signal( 2); a 3 state inverter buffer(3I3) for producing a latched output from the latched data(LD2) of the 3 phase inverter buffer(3I2); thereby removing an error of the latch circuit.