发明名称 3D interconnection process for electronic component packages and resulting 3D components
摘要 A device and method for interconnection packages in a stack. Each package encapsulates, for example a semiconductor chip containing an integrated circuit, which for example may be a memory. The packages (2) which have connecting pins (21) are mounted on support grid (4) which preferably act as a heat shunt, and are stacked and linked to each other with a resin coating (5). A stack (3) is cut out so that the pins on the packages and one edge of the grids are flush with faces (31, 32) of the stack (3). Connections between the packages themselves, and between the packages and stack connecting pads, are made on the faces of the stack. The connecting pads are where necessary fitted with connecting pins.
申请公布号 US5526230(A) 申请公布日期 1996.06.11
申请号 US19930124805 申请日期 1993.09.21
申请人 THOMSON-CSF 发明人 VAL, CHRISTIAN
分类号 H01L23/52;H01L25/00;H01L25/065;H01L25/10;H01L25/11;H01L25/18;(IPC1-7):H05K7/20 主分类号 H01L23/52
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