| 摘要 |
PURPOSE: To eliminate the need for the setting up of a memory storing pattern data for thinning out and to simplify the configuration by easily generating a thinned out clock signal corresponding to an optional reduction rate. CONSTITUTION: Let a reduction rate be m/n, then an arithmetic circuit 9 adds a value (d) (=m-n) to its own output OUT 1 and provides an output as a new output OUT 1 synchronously with the rising of a clock signal CLK. A comparator circuit 10 outputs the output signal OUT 2 of an H level to the arithmetic circuit 9 when the output OUT 1 reaches a value (n) or over. The arithmetic circuit 9 subtracts the value (n) from the output value OUT 1 synchronously with the rising of the clock signal CLK when the output signal OUT 2 is at an H level. Furthermore, an AND circuit 11 outputs a signal going to an H level only when the output signal OUT 2 is at an L level and the clock signal CLK is at an H level as a thinned out clock signal SCLK. |
