| 摘要 |
PURPOSE: To lock the delay of one clock without fail by providing a phase detecting means, voltage generating means and delay means and forcedly turning a voltage, which is generated by the voltage generating means when a power source is turned on, to a level expressing that voltage is set in the state of comparatively short phase difference. CONSTITUTION: Since a PMOS transistor 17 is turned off when an output signal/ POR of a power ON reset circuit 18 is turned to an 'H' level, according to both output signals/UP and DOWN from a phase detector 12, a voltage signal VCOIN gradually starts lowering from the 'H' level. With this reduction, the operating speed of a voltage controlled delay element 15 is decelerated as well, an internal clock RCLK of its output signal is synchronized with an external clock ECLK, and the DLL circuit is locked. Then, the voltage signal VCOIN takes a fixed value at that time point. As a result, the DLL is locked in the state of delaying the internal clock RCLK from the external clock ECLK for one clock. |
