发明名称 High-speed dual-buffered output circuit
摘要 In an output circuit for driving a load connected to an output terminal in accordance with an input signal input to an input terminal, the output circuit connects to the input and output terminals, a first output buffer which operates when activated; connects in parallel to the first output buffer, a second output buffer which, when activated, operates with driving ability higher than the first output buffer; and activates the second output buffer for a predetermined period when the input signal is input and, after the period, activates the first output buffer.
申请公布号 US5517129(A) 申请公布日期 1996.05.14
申请号 US19920920911 申请日期 1992.07.28
申请人 FUJITSU LIMITED 发明人 MATSUI, NORIYUKI
分类号 G11C11/417;G11C7/10;G11C11/409;H03K17/16;H03K19/0175;H03K19/0948;(IPC1-7):H03K19/003 主分类号 G11C11/417
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