发明名称 CMOS full duplex transmission-reception circuit
摘要 The data input/output circuit for full duplex communication includes a data accepting and sending circuit which has an input/output terminal connected to a processor provided within a digital apparatus, and which receives data from the processor, transmits the data and receives outside data through the input/output terminal, a reference circuit which divides a voltage level of the data transmitted from the data accepting and sending circuit and produces a divided voltage level, a differential receiving circuit which has one input terminal connected to the input/output terminal and another input terminal connected to the reference circuit, and which is not operated by a zero voltage difference between the input terminals when the data is transmitted from the input/output terminal but operated by a voltage difference between the input terminals when the data is received through the input/output terminal, the data being supplied to the processor of the digital apparatus, a reference circuit for generating an output impedance value of the data accepting and sending circuit, and a voltage regulation circuit for adjusting a power supply voltage to be applied to the data accepting and sending circuit so that the output impedance value is changed in accordance with the value of the output impedance. This data input/output circuit can be incorporated in an LSI of CMOS transistor structure and has a simple circuit arrangement capable of impedance matching with the transmission path.
申请公布号 US5514983(A) 申请公布日期 1996.05.07
申请号 US19940360325 申请日期 1994.12.21
申请人 HITACHI, LTD. 发明人 YOSHINO, RYOZO
分类号 G06F3/00;H03K19/00;H03K19/0175;H03K19/0185;H04B1/04;H04B1/40;H04L5/14;H04L25/02;(IPC1-7):H03K19/017 主分类号 G06F3/00
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