| 摘要 |
The apparatus includes an ALL transmission buffer(12) for storing and sending ATM cell, an ALL transmission controller(13) for sending the transmission clock signal to the transmission buffer(12) and for sending frame signal, clock signal and synchronous signal to an ATM, an ATM reception buffer(14) for receiving signals transmitted from the ALL transmission controller(13), an ALL reception controller(15) for generating the sent request signal, an ATM transmission buffer(19) for storing ATM cell, an ATM transmission controller(18) for sending ATM cell, frame signal, clock signal and synchronous signal to the ALL, and a ALL reception buffer(16) for receiving ATM cell and output control signal transmitted from the ALL reception controller(17). |
