| 摘要 |
PURPOSE: To obtain a flip-flop circuit used with a slow repetitive cycle by improving a delay time of the flip-flop so as to improve the performance of a computer system. CONSTITUTION: A dynamic flip-flop circuit (slave side) is made up of a circuit comprising a transfer gate TG3 and an inverter 14 and a feedback loop flip-flop circuit (master side) is formed by a circuit comprising inverters 12, 13 and a transfer gate TG2. Thus, a delay by contention of the inverters is avoided to attain high processing. Furthermore, a clock pulse signal shown in figure A is fed to the FF circuit. Thus, the width of a negative portion of the clock used by the master side to receive data is constant and a width of a positive portion of the clock used by the slave side to received data and to send the data is extended when the clock cycle is slow, and deterioration in the data of a dynamic FF of the slave side is not a problem even when the clock cycle is extended. |
