| 摘要 |
There is provided an image data partitioning circuit for use in a parallel image decoding system which is capable of a effective partitioning operation for a variable length coded image, thereby advantageously achieving a high speed decoding operation. The image data partitioning circuit comprises: N buffer, each coupled to the respective decoding module for storing a partitioned variable length coded image to be processes thereby, respectively; first detector for detecting a starting position of the horizontally sliced data and generating a starting position detection signal; second detector for detecting a vertical position of the horizontally sliced data and for generating a vertical position detection signal; and partitioning device responsive to the starting position detection signal and the vertical position signal for partitioning the variable length coded image and for sequentially coupled the partitioned data of the variable length coded image to the N buffers.
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