| 摘要 |
The machine has multiple memory cells (7), each connected to a clock line (CK) which controls timing of read and write operations in the memory. The memories are configured so that after each write operation, a read operation can occur only after a predetermined time delay. The time delay is greater than the maximum propagation delay, but less than a clock period. A gate circuit (17) drives a switch (19) that is open as the memory is updated and closes after a set delay. The gates are D-type flip-flops that are activated by the leading edge of the clock pulse, and the switches are closed on the trailing edge of the clock pulse. The switches are tri-state devices with a high output impedance. |
