| 摘要 |
PURPOSE: To provide a semiconductor storage device long in data retention time by maintaining the word line potential of the DRAM in the nonselection state at a negative value. CONSTITUTION: In the nonselection state of the memory cell of the line decoder where the address signals, Xi , Xj , and ϕXa , and the precharge signal ϕp fall, for example, the NFET 8a is off and the PEET 3a is on; the internally-high power source voltage Vpp is fed; the NFET 9a is on whose threshold is higher than those of the NFET 7, 8, and 8a ; and the word line WLa is fed with a voltage such as the internally-low voltage Vw to be kept at a negative potential such as -0.5V. When the negative bias potential of the memory cell substrate is held at a low voltage such as -0.5V or so in order to reduce the reverse leak current of the PN junction and to thereby elongate the data retention time of the memoty cell, the drop of the threshold of the MOSFET is less than 0.5V and the potential the word line becomes negative to a greater extent than the drop of the threshold, reducing the sub-threshold current and elongating the data retention time of the DRAM without increasing the chip area. |
