MEDIUM VOLTAGE GENERATING CIRCUIT OF SEMICONDUCTOR INTEGRATED CIRCUIT

摘要

The circuit uses a drive circuit which includes an NMOS transistor (Q8) in between a PMOS transistor (Q4) and a ground voltage (Vss) and another PMOS transistor (Q7) in between a second NMOS transistor (Q3) and a supply voltage (Vcc). It receives an intermediate voltage input (VM) at the gate of its first NMOS transistor and its second PMOS transistor. The generator also uses a bias circuit (41) with the same set up as the drive circuit which receives the intermediate voltage via its connections with the drive circuit at the gates of a third NMOS transistor (Q6) and a fourth PMOS transistor (Q5). The circuit controls generation of excessive current from drive circuit, and ensures high reliability and restoration capability of intermediate voltage.