| 摘要 |
PURPOSE:To lessen the size in the arrangement direction of a cell and to contrive an increase in the number of input/output pins by a method wherein basic cells respectively consisting of a pair of a P-MOS transistor and an N-MOS transistor, which are formed into the same form, are arranged regularly at a transistor region for input and logic. CONSTITUTION:An output region of a semiconductor integrated circuit is constituted of a P-MOS transistor 6 for output and an N-MOS transistor 7 for output and a region 11 for input and logic is constituted of basic cells 12 for input and logic. When an input/output buffer cell 5 constituted like the above way is used as an input buffer, a P-MOS transistor 13 for input and logic and an N-MOS transistor 14 for input and logic are connected to the cell 5. When the cell 5 is used as an output buffer, the MOS transistors 6 and 7 are connected to the cell 5 and when the cell 5 is used as a tri-state output buffer and an input/output bidirectional buffer, the MOS transistor 6 is connected to the MOS transistor 7 and at the same time, is connected to the MOS transistor 13 as well. The MOS transistor 14 is connected to the MOS transistor 7 and at the same time, is connected to the MOS transistor 13 as well. Thereby, the size in the arrangement direction of the cell 5 is reduced and the number of input/ output pins can be increased. |
