| 摘要 |
<p>A memory system for coupling memory circuits (650) to controller circuits (620) in a data processing system. The controller circuit (620) transmits command, data and address signals via a single bus (622) and is responsive to selected data and address signals on the bus (622). The memory circuits (650) selectively transfer data to and from the controller circuit (620) in response to selected command and address signals. A command decode circuit (632) in each memory circuit (650) preferably includes means for incrementing the program counter (634) after each memory operation in response to selected command signals, thereby enabling a number of sequential memory operations in response to a single command. At least one memory circuit (650) is preferably a plug-in read-write memory module having a power switching circuit (648) for providing continuous power from the main power bus (628) of the data processing system or a battery (646) housed within the plug-in module.</p> |
