| 摘要 |
PURPOSE:To enable high-speed processing and reduce the circuit scale of the two-dimensional discrete cosine transform arithmetic circuit which is used for high-efficiency encoding. CONSTITUTION:In an arithmetic stage of DCT, Hadamard transformation and multiplication are performed in order, and an arithmetic stage of IDCT is equipped with a conversion block 1 consisting of a multiplication part 5 which performs multiplication and Hadamard transformation in order and a Hadamard transformation part 6, a memory block 2 which temporarily stores input/output data in the arithmetic stage of the conversion block 1, an input/output processing back 3 which performs preprocessing or postprocessing such as cumulative addition and subtraction, etc., of input/output data of the conversion block 1, and a control block 4 which controls the multiplication coefficient of the conversion block 1 in the arithmetic stage of DCT or IDCT, controls the writing and reading of the memory block 2, and also controls the input/ output processing block 3. |
