| 摘要 |
<p>A synchronous semiconductor memory device has an M-bit I/O configuration memory device mode and an Mx2<k>-bit I/O configuration memory device mode. In the former mode, n bits whose transition frequencies are smaller are selected from an m-bit internal address and are used to access a memory section (60 SIMILAR 63, 60' SIMILAR 63'), while the other k (= m-n) bits whose transition frequencies are larger are selected from the m-bit internal address to select one of 2<k> groups of internal data lines (D0 SIMILAR D7) of the memory section and connect them to some of data input/output pins (P0 SIMILAR P3). In the latter mode, n bits whose transition frequencies are larger are selected from the m-bit internal address and are used to access the memory section, while the 2<k> groups of the data lines are connected to all the data input/output pins. <MATH></p> |
