| 摘要 |
<p>PURPOSE:To obtain a memory device of a single power supply and one transistor type by setting bias conditions for each wirings corresponding to operation, by performing writing and erasing data by injection and extraction of electrons by FN tunneling. CONSTITUTION:In this memory array constitution, both bit lines and source lines are hierarchized to main wirings M-DBL, SBL and sub-wirings S-DBL, S-SBL, selecting transistors ST are arrange between the main wirings and the sub-wirings respectively, and memory cell transistors MT are arranged between sub-wirings. And erasing operation is performed by extracting electrons in floating gate from drain sides by FN tunneling, and writing operation is performed by injecting electrons in a floating gate from a whole surface of a channel by FN tunneling. For example, erasing is performed by impressing -14V to a selected word line WL2, 3.3V to all main bit lines DBL, 5V to selected gate lines SL1, SL2. At the time, oV is impressed to other lines and a common source line SBL.</p> |
