发明名称 |
Generally-diagonal mapping of address space for row/column organizer memories |
摘要 |
A method for storing data in a generally-diagonal pattern in blocks of a flash EEPROM array by which the least number of memory cells are affected by a failure of either a row conductor or a column conductor, and apparatus for addressing the flash array to produce such a generally-diagonal storage pattern. The arrangement allows the simplest forms of error detection and correction circuitry to be utilized.
|
申请公布号 |
US5490264(A) |
申请公布日期 |
1996.02.06 |
申请号 |
US19930130023 |
申请日期 |
1993.09.30 |
申请人 |
INTEL CORPORATION |
发明人 |
WELLS, STEVEN;WINSTON, MARK |
分类号 |
G11C29/00;(IPC1-7):G06F12/00 |
主分类号 |
G11C29/00 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|