| 摘要 |
PURPOSE:To achieve high integration and performance without making complex an element structure and a manufacturing process by short-circuiting between a source and a drain of a selected MOS transistor by conductor wiring for writing data. CONSTITUTION:Those memory MOS transistors M11-M18 and M2 l-28 which are adjacent each other share source and drain to form a NAND-type memory cell which are connected in series. All of the MOS transistors M11-M18 and M21-M28 are of enhancement type and the source and drain of the selected MOS transistors out of them are short-circuited by conductor wiring for writing data, thus virtually performing data read which is similar as in D type. Also, the problem of leak increase in an element separation region due to the exudation of the impurity at a channel region can be solved without making complex an element structure and a process. |
