发明名称 AUTOMATIC SAMPLING CLOCK ADJUSTING METHOD AND ITS CIRCUIT
摘要 PURPOSE:To provide a sampling clock with an optimum phase by automatically adjusting a sampling clock phase in a video signal processing circuit sampling an analog video signal by a clock pulse. CONSTITUTION:An input analog video signal S1 is made a binary signal by a binary signal making circuit 101, and the binary signal is made the sampling clock, and a zero signal and a one signal of a phase variable clock S3 formed in a clock oscillation circuit 107, a delay circuit 108 and a selector 109 are sampling-counted and compared, and the phase of the clock S3 is adjusted by the selector 109 so that the difference becomes zero, and the sampling clock signal S3 with the phase suitable for the input analog video signal S1 is obtained.
申请公布号 JPH0822276(A) 申请公布日期 1996.01.23
申请号 JP19940158339 申请日期 1994.07.11
申请人 FUJITSU GENERAL LTD 发明人 HASHIGUCHI KOTA
分类号 H04N5/06;G06T1/00;G09G3/20;G09G5/12;H03L7/00;H04N7/24;H04N19/00;H04N19/423;H04N19/59;H04N19/80 主分类号 H04N5/06
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