发明名称 Priority encoder
摘要 <p>The carry-line (2) comprises a plurality of MOSFETs (N15-N0) connected in series. MOSFETs (P15-N0) precharge each node (3-15 to 3-0) when they receive precharge signals /PR. In the case of high-order priority designated mode, when input signals (Q15-Q0) are given for turning on MOSFETs located between one end of the high-order bit side of the carry-line (2), the control circuit (5a) discharges the intermediate node (3-8) separately from the carry-line (2). In the case of low-order bit priority designated mode, when input signals (Q15-Q0) are given for turning on MOSFETs located between one end of the low-order bit side of the carry-line (2) and the intermediate node (3-8), the control circuit (5b) discharges the intermediate node (3-8) separately from the carry-line. &lt;MATH&gt;</p>
申请公布号 EP0692761(A1) 申请公布日期 1996.01.17
申请号 EP19950111002 申请日期 1995.07.13
申请人 KABUSHIKI KAISHA TOSHIBA 发明人 ISHII, YASUHIRO;NAKATA, SHIGEHARU
分类号 G06F7/00;G06F7/74;H03M7/00;(IPC1-7):G06F7/00 主分类号 G06F7/00
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