发明名称 Multiple clocked dynamic sense amplifier
摘要 A method and circuit is provided for reading a memory array which utilizes multiple clocking signals during one read cycle to enable a dynamic sense amplifier to read data from the memory array. A dynamic sense amplifier is connected to an input line, a complementary input line, and a latch. A first equilibrating signal is input into the sense amplifier, followed thereafter by a first clocking signal. The first clocking signal enables the sense amplifier to read data on the input line and complementary input line. While the sense amplifier reads the data, the sense amplifier is isolated from the input and complementary input lines. Based upon the data read by the sense amplifier, an output state is provided for the latch. After reading the data, the sense amplifier is reconnected to the input and complementary input lines. A second clocking signal then enables the sense amplifier to read the data on the input and complementary input lines a second time, and the sense amplifier is isolated from the input and complementary input lines. The output state of the latch may or may not change based upon the data read by the sense amplifier the second time.
申请公布号 US5485430(A) 申请公布日期 1996.01.16
申请号 US19940306527 申请日期 1994.09.15
申请人 SGS-THOMSON MICROELECTRONICS, INC. 发明人 MCCLURE, DAVID C.
分类号 G11C7/06;(IPC1-7):G11C8/00;G11C7/00 主分类号 G11C7/06
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