| 摘要 |
<p>PURPOSE:To attain high speed processing under a high capacity independently of number of transmission destination LSI with respect to the serial interface circuit to send/receive data between a microprocessor and the LSIs or between the LSIs. CONSTITUTION:A serial interface transmission section 3 at a transmitter side sends bit serial data comprising plural sets of data each comprising a frame pattern, address data representing data structure of transmission data and the transmission data themselves and sends a frame pulse being active during a period of the frame pattern. A receiver side detects the frame pattern from a frame pulse FP and a bit serial signal received by a frame synchronization detection section 4 to generate a head timing FT of the frame, and an address extract section 5 receives address data from the bit serial signal based on a frame timing. Then a data reception section 6 receives a data bit addressed to itself from the bit serial data based on the frame head timing when the data bit addressed to itself is included in the reception data of a data structure represented by the address.</p> |
