| 摘要 |
PURPOSE:To improve arithmetic processing efficiency by dividing an arithmetic processor into plural parts to attain the independent arithmetic processing only with a divided unit of the processor and therefore securing the effective use of an arithmetic processing part of a remaining half-word part even in a half- word operation mode. CONSTITUTION:An operator is divided into a high-order arithmetic unit 3 and a low-order arithmetic unit 4, and the high-order and low-order data of a store register 1 for data to receive operations and an arithmetic data store register 2 are supplied to the units 3 and 4 respectively. When the arithmetic mode is set in a division mode, the independent half-word data are supplied to the high-order and low-order positions of both registers 1 and 2. Then calculation is executed. Thus an arithmetic result flag S1 of the unit 3 is stored to a high- order arithmetic state register 63. While an arithmetic result flag S2 of the unit 4 is stored to a low-order arithmetic state register 64. The arithmetic results are stored to an arithmetic store register 5. In a full-word arithmetic mode, those arithmetic result flags are stored to a register 61. |
