Apparatus and Method for Clock Alignment and Switching

摘要

In a telecommunication system (figure 1) having multiple timing subsystems (14, 16 and 18) receiving and distributing redundant timing signals, there i s provided a circuitry for aligning first and second redundant timing signals (CLOCK A and CLOCK B) and switching therebetween. The circuitry includes a selecting and switching circuitry for receiving the first and second redunda nt timing signals (CLOCK A and CLOCK B) and designating one of the redundant timing signals as ACTIVE and the other as INACTIVE, and providing the ACTIVE timing signal as an output timing reference signal. The selecting and switching circuitry further switching the ACTIVE and INACTIVE timing signal designation and output timing reference signal in response to detecting faul t or a clock switching command. The ACTIVE timing signal is provided to a firs t delay path (DELAY PATH A) having a programmable delay value, which delays it and produces a first output timing signal. A second delay path (DELAY PATH B ) receives the INACTIVE redundant timing signal and produces a second output timing signal. The circuitry further includes a phase detector (50) which receives the ACTIVE and INACTIVE output timing signals and generates a statu s signal indicative of the phase relationship therebetween.