发明名称 |
Single ram multiple-delay variable delay circuit |
摘要 |
A multiple-delay variable delay circuit uses a random access memory (RAM) array to provide adjustable delay of a block of input data, such as previously necessitated use of an extensive shift register configuration. A single RAM array, having a given capacity, is used to economically provide individual delays to a plurality of blocks of input data, with the aggregate of the individual delays not exceeding the capacity of the single RAM array. Time-shared use of a high speed RAM enables simultaneous single-port processing of data blocks, with delay control circuits providing utilization of separate portions of the RAM capacity, to provide individual delays resulting from successive read/write cycles utilizing a desired total of incremental delays. Simplified delay control circuits provide manufacturing and operating economies with single-port or multi-port RAM arrays.
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申请公布号 |
US5479128(A) |
申请公布日期 |
1995.12.26 |
申请号 |
US19940213852 |
申请日期 |
1994.03.16 |
申请人 |
INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE |
发明人 |
JAN, YUNG-JUNG;HUANG, PO-CHUAN;YANG, CHING-HSIANG |
分类号 |
G11C8/04;(IPC1-7):G11C7/00 |
主分类号 |
G11C8/04 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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