| 摘要 |
<p>PURPOSE:To provide a memory access controller, which can operate fast while suppressing the power consumption, even for a ROM and a RAM. CONSTITUTION:The high-order address of an address outputted so as to access a ROM 102 by a CPU 101 is halved into 1st and 2nd address parts 11b and 11c. A circuit 105 generates chip-enable signals CE-N1 and CE-N2 on the basis of the 1st address part. A circuit 110 generates an output-enable signal OE-N on the basis of a read command from the CPU, the signal CE-N2, and the 2nd address part 111c. Consequently, the chip-enable signal is validated even in a specific address area other than a ROM address area.</p> |
