| 摘要 |
A vertical sync signal circuit for producing a stable sync signal is disclosed. A first frequency divider and a first window circuit generate a sync output pulse PC having the same period as the vertical sync signal contained in the TV signal and a first window signal W1. A reference signal generator generates a reference signal VR in synchronism with the vertical sync signal VS being input. A second frequency divider and a second window circuit generate a second window signal W2 wider than the first window signal W1. A third frequency divider discriminates the period of the reference signal VR on the basis of the first window signal W1 and the second window signal W2, and selects the sync output pulse PC1 or the reference signal VR. The sync signal CVD having the same period as the sync output pulse PC or the reference signal VR, as the case may be, is produced through an output switching circuit. As a result, a sync signal CVD in synchronism with the vertical sync signal VS is output always in a stable manner.
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