发明名称 Programmable logic device routing architecture
摘要 An integrated electronic circuit architecture has low leakage current and capacitance and includes a user-programmable integrated circuit design (110) having a plurality of designed conductors (112, 118) and a plurality of designed functional circuit blocks (e.g., 12,14, etc.). In the architecture, a plurality of user-programmable antifuse elements (e.g., 26, 28, 30, etc.) connect to the plurality of conductors (112, 118) and the plurality of functional circuit blocks (12, 14, 16, etc.). The plurality of user-programmable antifuse elements (e.g., 26, 28, 30, etc.) connect the plurality of conductors (112, 118) with one another and to the plurality of functional circuit blocks (12, 14, 16, etc.). The plurality of conductors (112, 118) is segregated into at least two groups including a first group of conductors and a second group of conductors. Antifuses (26, 28, 32) in the first group of conductors are selectively depopulated to reduce capacitance and leakage associated with their placement in the user-programmable integrated circuit (110), while the conductors of the first group of conductors permit access to conductors in the second group of conductors. Segmentation transistors (114, 122, 136) separate the first group of conductors from the second group of conductors.
申请公布号 US5469078(A) 申请公布日期 1995.11.21
申请号 US19940177891 申请日期 1994.01.06
申请人 发明人
分类号 H03K19/177;(IPC1-7):H03K19/177 主分类号 H03K19/177
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