发明名称 RESETTING CIRCUIT AND RESETTING METHOD
摘要 <p>PURPOSE:To securely reset an object arithmetic means while protecting the contents of a peripheral circuit. CONSTITUTION:The resetting circuit 1 which outputs a reset signal to the arithmetic means 6 to initialize the operation of the arithmetic means 6 is equipped with a reset signal generating means which generates the reset signal to be outputted to the arithmetic circuit 6, a state detecting means 3 which detects the occupation state of a data bus by the arithmetic means 6, and an output decision means 4 which decides whether or not the reset signal generated by the reset signal generating means is outputted to the arithmetic means 6 on the basis of a request to output the reset signal and the detection result of the state detecting means 3; and the output decision means 4 outputs the reset signal to the arithmetic means 6 on condition that the state detecting means 3 detects the arithmetic means 6 not occupying the data bus when the request to output the reset signal is made.</p>
申请公布号 JPH07295687(A) 申请公布日期 1995.11.10
申请号 JP19940110529 申请日期 1994.04.25
申请人 CASIO COMPUT CO LTD 发明人 HIROYA TAKAYUKI;ORIMOTO TAKASHI;MORIYA KOJI;KANEKO KATSUYOSHI;WATANABE KAZUYOSHI
分类号 G06F1/24;(IPC1-7):G06F1/24 主分类号 G06F1/24
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