| 摘要 |
PURPOSE:To obtain the semiconductor integrated circuit device which controls the input/output timing of signals of a desired internal circuit in synchronism with an external clock signal without any phase delay. CONSTITUTION:An internal clock signal CLKI is inputted from a PLL circuit 1 to an internal block circuit NKn through an internal signal transmission line L1. A feedback signal PLLB is fed from the internal block circuit NKn back to the PLL circuit 1 through a feedback line L2 which is as long as the signal line L1. A phase comparing circuit 4 detects the phase difference between the PLLO and PLLB and outputs a phase comparison voltage signal S4, and a 1/2 voltage converter 5 halves the voltage of the phase comparison voltage signal S4 and outputs a converted voltage signal S5. A voltage control delay circuit 6 delays the external clock signal CLK.EXT by the phase difference (feedback signal propagation delay time) prescribed with the converted voltage signal S5 and outputs the external clock delayed signal DCLK.EXT to the PLL circuit 1. |
