发明名称 TIMING RECOVERY CIRCUIT
摘要 <p>PURPOSE:To extend a frequency error range to be traced by controlling accurately a phase of sampling at A/D conversion with respect to the timing recovery circuit for a digital transmission reception circuit. CONSTITUTION:In a digital reception circuit comprising an A/D converter 1 sampling a received signal and converting the sampled signal into a digital signal, an impulse response estimate section 3 estimating an impulse response of the digital signal to output a pre-cursor as timing information, and a timing recovery circuit 4 generating sampling phase control information to the A/D converter 1 depending on the timing information, the timing recovery circuit 4 is made up of a loop filter 37 eliminating a high frequency component of the impulse response estimate section 3, an accumulator 40 accumulating outputs of the loop filter 37, and a comparator section 41 identifying the accumulated value of the accumulator 40 with a prescribed threshold level to output sampling phase control information and subtracting the accumulated value by the accumulator 40 by the threshold level.</p>
申请公布号 JPH07264249(A) 申请公布日期 1995.10.13
申请号 JP19940054281 申请日期 1994.03.25
申请人 FUJITSU LTD 发明人 AWATA YUTAKA;KOIZUMI NOBUKAZU;OOTOMO YASUHISA;TSUNOISHI MITSUO
分类号 H03M1/12;H03H21/00;H03L7/06;H04B3/06;H04J3/06;H04L7/00;H04L7/02;H04L25/03;(IPC1-7):H04L25/03 主分类号 H03M1/12
代理机构 代理人
主权项
地址