| 摘要 |
PURPOSE: To provide a frequency locked loop which has small sensitivity to variation in phase. CONSTITUTION: This frequency locked loop has a phase comparator 10 which receives a 1st and a 2nd period signal and has a 1st output for sending a pulse out when the 1st signal is precedent in phase to the 2nd signal and a 2nd output for sending a pulse out when the 1st signal is delayed behind the 2nd signal, an oscillator 20 which sends the 2nd signal out, a counter 22 which determines the frequency of the oscillator 20 and has an increasing input and a decreasing input, and sampling circuits 24, 25, 27, and 32 which transmit an (N)th pulse of an input increasing when a pulse is generated with the 1st output or 2nd output of the comparator 10 or an input decreasing when the pulse is generated with the other output. |
