| 摘要 |
PURPOSE:To prevent soft errors a memory cell due to a ray, to enlarge a power supply line forming region and to reduce the area of a memory cell. CONSTITUTION:The drain (P-type diffusion layer 68) of a pMOS transistor 7, the drain (N-type diffusion layer 71) of an nMOS transistor 9 and a polysilicon layer 77 are interconnected with a tungsten layer 80 which does not require a contact hole for the connection to the other layer, and also the drain (P-type diffusion layer 70) of a pMOS transistor 8, the drain (N-type diffusion layer 73) of an nMOS transistor 10 and a polysilicon layer 76 are interconnected with a tungsten layer 81 which does not require a contact hole for the connection to the other layer. |
