发明名称 BiMIS logic circuit
摘要 A BiMIS circuit has first and second input terminals; first and second output terminals; a first bipolar transistor having a collector receiving a first potential, an emitter connected to the first output terminal, and a base connected to the second output terminal; a second bipolar transistor having a collector connected to the first output terminal and an emitter receiving a reference potential; a first MIS transistor circuit including MIS transistors, connected to the base and the collector of the first bipolar transistor and the first input terminal, and turned on or off depending on a potential of the first input terminal; and a second MIS transistor circuit including MIS transistors, connected to the base of the first bipolar transistor, the second input terminal and the base of the second bipolar transistor, and turned on or off depending on a potential of the second input terminal. The BiMIS circuit includes at least one of: a capacitor having one terminal connected to the first input terminal and the other terminal connected to the base of the second bipolar transistor; a discharging circuit connected to the base of the first bipolar transistor for discharging the base; and a potential setting circuit connected to the base of the second bipolar transistor for setting a potential of the base at a predetermined level.
申请公布号 US5457413(A) 申请公布日期 1995.10.10
申请号 US19930130661 申请日期 1993.10.01
申请人 NEC CORPORATION 发明人 OGURI, TAKASHI
分类号 H03K17/567;H03K19/013;H03K19/08;H03K19/0944;(IPC1-7):H03K19/02 主分类号 H03K17/567
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