| 摘要 |
Pseudo-exhaustive self-testing of an electronic circuit (10), containing groups of combinational elements (141,142, 143 . . . 14n), is accomplished by first partitioning the groups of combinational elements into sub-cones having no more than w inputs each by designating appropriate nodes ("test points") in each cone as the output of a sub-cone. A set of test vectors {a1, a2 . . . aw, b1, b2 . . . bw} is then generated (via an internal generator 74) such that when the vectors are applied to the sub-cones (141a, 141b . . . . 14ij), each sub-cone will be exhaustively tested. Each of the inputs of the sub-cones is assigned to receive a vector such that the vectors received at the inputs are linearly independent. The subset of vectors is applied through each of a plurality of pseudo-exhaustive self-test (PEST) flip-flop circuits (88) and through the test points to test the circuit. The PEST flip-flop circuits 88 also serve to advantageously compact and observe the response data produced by each sub-cone (14ij) with that of an upstream sub-cone. |
