BIT SYNCHRONIZATION CIRCUIT HAVING NO CLOCK RECOVERY

摘要

The circuit comprises the first and the second D Flip-Flop which latches the input clock and the converted input clock, the first frame synchronization circuit which outputs in-frame A signals with the assurance of the frame synchronization by inputting the inverted clock and the output data of the first D Flip-Flop, the second frame synchronization circuit which outputs in-frame B signals with the assurance of the frame synchronization by inputting the input clock and the output data of the second D Flip-Flop, a data selection unit which outputs selectively the output data of the D Flip-Flops, and a clock selection unit which outputs selectively the input clock and the inverted clock.