摘要 |
<p>A computer system (15) incorporating a pipelined bus (20) that maintains data coherency, supports long latency transactions and provides processor order is described. The computer system (15) includes bus agents (2, 4, 6, 8, 10, 12, 14) having in-order-queues (100) that track multiple outstanding transactions across a system bus (20) and that perform snoops in response to transaction requests, providing snoop results and modified data within one transaction. Additionally, the system (15) supports long latency transactions by providing deferred identifiers during transaction requests that are used to restart deferred transactions.</p> |