| 摘要 |
PURPOSE:To provide a clock signal generation circuit in which a clock signal is easily managed, the occurrence of clock skews is easily and surely prevented and a through-current is completely prevented. CONSTITUTION:The generation circuit is provided with a master clock signal generation circuit 2M that generates a high level signal MCLK based on a low level clock signal CLK and a low level signal SCLK and generates a low level signal MCLK based on a high level signal CLK, a slave clock signal generation circuit 2S that generates a low level signal SCLK based on a low level signal CLK and generates a high level signal SCLK based on a high level clock signal CLK and a low level signal MCLK, and also a delay generation circuit 3M whose delay time is set optionally to delay the signal SCLK outputted from the signal generation circuit 2S by a desired time and to provide the delayed signal to the signal generation circuit 2M, and a delay generation circuit 3S whose delay time is set optionally to delay the signal MCLK outputted from the signal generation circuit 2M by a desired time and to provide the delayed signal to the signal generation circuit 2S. |
