Ball grid array packages for high speed applications

摘要

A package and packaging technique for enhancing performance of critical chips within an electronic device, wherein the critical chips comprise an integrated circuit. The package includes a main package incorporating a first integrated circuit coupled to a substrate board. At least one package having a second integrated circuit is mounted to the main package in order to reduce (i) propagation delay for data to transfer between critical chips within the main package and one of the plurality of packages or between the critical chips within the plurality of packages and (ii) total footprint area. The method for implementing such a package including the steps of packaging the first and second integrated circuits and electrically coupling these integrating circuits together in a mounted position.