Low power analog absolute differencing circuit and architecture

摘要

A low power analog absolute differencing circuit includes an integrating amplifier with an input node connected to a common integration line. The common integration line is connected to a set of analog comparison circuits to form an analog vector absolute differencing circuit row. Each of the analog comparison circuits compares a first analog signal to a second analog signal to produce an absolute difference signal. The absolute difference signal from each analog comparison circuit is transmitted in the form of charge drawn from the common integration line. The integrating amplifier provides an integration sum corresponding to the sum of the absolute difference signals. The analog absolute differencing architecture includes a set of analog vector absolute differencing circuit rows arranged to form an analog absolute difference computing array. The analog absolute difference computing array is loaded with a data block input array and a data frame input array. The data block input array inputs a first set of analog signals corresponding to a first set of data. The data frame input array inputs a second set of analog signals corresponding to a second set of data. The integrating amplifiers of the analog vector absolute differencing circuit rows of the analog absolute difference computing array constitute a distance integration array. A distance evaluation block takes as input the set of distances computed by the distance integration array and evaluates these distances to provide a single output, usually an address of a single row of the distance integration array.