| 摘要 |
<p>A divider of a high radix nonrestoring type or a floating-point coprocessor and vector processor including the divider, comprising means (10) for deriving a multiple of a divisor from the information based on the predictive quotient, a processing means (11) for producing output resulting from an arithmetic operation between the multiple of the divisor and a dividend and outputting the sign bit indicating the sign of the result of operation, a decoding means which begins to decode the result of operation during the generation of the sign bit and outputs a decode signal indicative of either the result of operation or its complement depending on the sign bit, and a means (14) for generating the predictive quotient according to the output of the decoding means. The decoding is started before the most significant bit (sign bit) results from the arithmetic operation, and thereafter, the result of the decoding is selected as soon as the most significant bit (sign bit) is determined. Thereby, the unwanted delay (t alpha ) due to thetime required for carries can be absorbed by a decoding time (t beta ), and the operational time of the divider can be reduced. <IMAGE></p> |
