| 摘要 |
PURPOSE:To properly adjust the output timing of the waveform data without enlarging a circuit scale by providing a timing adjustment means revising the storage position of the phase data read out by an address generation means in a time division channel according to the timing when an address is required to be generated. CONSTITUTION:A RAM 32 writes the phase data PD in a full adder 31 in the position of a RAM address RADR from the full adder 37, and reads out the phase data PD from the position of the RAM address RADR from the full adder 37 to output to latch circuits 33 and 34. A counter 35, an AND circuit 36 and the full adder 37 add an offset value OFS corresponding to a delay time to a count value from the counter 35 at the prescribed timing in one clock of an operation clock to output. When the offset value PFS is a negative value, the output timing of the phase data PD is delayed by the time corresponding to the delay time from the RAM 32, and inversely, when a positive value, the output timing is advanced. |
