发明名称
摘要 A device for testing a plurality of functional blocks such as RAM macros (13-1 through 13-m) in a semiconductor integrated circuit inputs plural kinds of testing signals necessary for testing the functional blocks from the exterior, and stores the testing signals to one register (11) or one latch to supply the testing signals in common to each of the functional blocks via a testing signal bus (AT,DIT,WET,BST). Thus, the plural functional blocks concurrently operate, and output their response signals. A multiplexor (15) selects one of those response signals and outputs it as the test output signal of the corresponding functional block. <IMAGE>
申请公布号 EP0558231(A3) 申请公布日期 1995.07.12
申请号 EP19930301137 申请日期 1993.02.17
申请人 NIPPON ELECTRIC CO 发明人 OHKAWA SHIN-ICHI
分类号 G11C11/413;G01R31/3185;G11C11/401;G11C29/00;G11C29/02;G11C29/28;G11C29/38;G11C29/56;(IPC1-7):G01R31/318 主分类号 G11C11/413
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